Technical Field
The present invention generally relates to field effect transistors and, more particularly, to the fabrication of planar field effect transistors that have inner spacers and no substrate channel path.
Description of the Related Art
A gate-all-around field effect transistor (FET) design can provide a high degree of electro-static control to help scale devices to ever-smaller dimensions. However, forming such devices on bulk semiconductor substrates shows short-channel effects. In addition, parasitic capacitance becomes a significant design difficulty.
In particular, when forming a gate-all-around FET, a stack of channel structures may be formed, but the underlying substrate can create a short-circuit between source/drain regions when the structures are very small. This causes the FET to perform poorly, with large currents even when the device is not turned on.